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Capacitors

The NPN BJTs are tested in the lab using ICS, an automated testing program. For more information, see Testing.

Capacitors

Theory

Each type of capacitor has been implemented with 3 different geometries so that one can extract the capacitance due to the corners and edges.

C = Carea + Cperiphery + Ccorners

Capacitance is given by

Cox = εA/d

Where

ε = dielectric constant of oxide
A = area of capacitor
d = thickness of oxide

Each layer will have a different oxide thickness and/or quality, which will result in different oxide capacitances.

Under a particular bias polarity, a depletion layer will form in the silicon, adding another capacitor in series with the oxide capacitor. The differential capacitance, Cd, of the semiconductor-space charge region is

Cd = εA/d

Where

ε = dielectric constant of silicon
A = area of capacitor
d = thickness of depletion region

The total capacitance is

Ctot = (Cox * Cd)/(Cox + Cd)

Here is a typical C-V curve for a MOS capacitor on an n-type substrate with V_aluminum applied to an aluminum contact on top of the oxide, with the substrate held at ground.

It is possible to model the capacitors by separating the capacitance into center and edge effects. The equations are similar to those used for modeling the p-n junction capacitance.

The total capacitance per area is

Ctotal = P * Cedge + A * Carea,

where P equals the perimeter and A equals the area. Note that the units of Cedge and Carea are pF/μm and pF/μm2, respectively.

By using two of the capacitors, it is possible to solve for P and A. The square capacitor is 300 x 300 μm, the round capacitor radius equals 150 μm, and the finger capacitor has a center region of 100 x 100 μm and twelve 20 x 100 μm fingers.

For Additional Information Consult:

  • Badih El-Kareh and Richard J. Bombard, Introduction to VLSI Silicon Devices, (Kluwer Academic Publishers, Hingham, Mass., 1986), pp. 296-328.
  • Arthur B. Glaser and Gerald E. Subak-Sharpe, Integrated Circuit Engineering, (Addison-Wesley, Reading, MA, 1979), pp. 80-94.
  • Ben G. Streetman, Solid State Electronic Devices, (Prentice-Hall, Englewood Cliffs, NJ, 1980), pp. 319-321.
  • K. H. Zaininger and F. P. Heiman, "The C-V Technique as an Analytical Tool," Solid State Technology, 13(5), pp. 49-56, (1970); 13(6), pp. 46-55, (1970).

Devices

BJTs

Capacitors

Contact Resistance

Control Structures

Diodes

Inverters

Integrated Circuit Cells

Misalignment Structures

Miscellaneous FETs

nMOSFETs

pMOSFETs

Resistors


Device Cell


LASI was used for mask layout.

The mask set is currently under revision 1998: Dane Sievers, which is a minor redesign of revision 1994: Ron Stack. All revisions are based on the work of revision 1991: Kevin Tsurutome.


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University of Illinois Urbana-Champaign

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